(1) Field of the Invention
The present invention relates to a semiconductor integrated circuit device whose patterns are formed using a phase-shifting mask. More particularly, the invention relates to a semiconductor integrated circuit device having electrode wires arranged to achieve a high degree of integration.
(2) Description of the Prior Art
One way of forming integrated circuit (IC) patterns using a phase-shifting mask involves locating phase shifters in apertures of a photomask to ensure that transmitted exposure light beams are 180 degrees out of phase between adjacent patterns whereby fine line patterns of high resolution are formed (known as the Levenson arrangement). The theory of pattern formation based on the Levenson arrangement is described in IEEE Transactions on Electron Devices, ED-29, pp. 1828-1836, 1982. This technique has made possible the formation of patterns with their fine lines made narrower than the wavelength of exposure light.
Next, a conventional example using the technique above is described in detail below with reference to FIGS. 3 and 4.
FIG. 3 is a plan view of wire electrodes in a conventional semiconductor integrated circuit device. In FIG. 3, wire electrodes 202, 203, 204 and 208 are part of first-layer IC elements including MOSFETs formed on a semiconductor substrate. The wire electrodes 204 and 208 are formed using a zero-phase pattern (.phi.=0) while the wire electrodes 202 and 203 are formed using a .pi.-phase pattern (.phi.=.pi.). The distances between the wires are minimized according to the principle of phase-shifting mask exposure.
FIG. 4 is a cross-sectional view taken on line Y1-Y1' in FIG. 3. As shown in FIG. 4, a silicon substrate 200 carries on it MOSFETs including a gate oxide film 231, gate electrodes 211, high-density impurity regions 210 (source and drain regions), and an isolation oxide film 209.
On the MOSFETS are a first interlayer insulating film 212, first-layer wire electrodes 202, 203, 204 and 208; a second interlayer insulating film 213, and a second-layer wire electrode 206 stacked one upon another. The high-density impurity regions 210 and first-layer wire electrodes 202 and 208 are interconnected by plug electrodes 201 each penetrating through the interlayer insulating film 212; the first-layer wire electrode 208 and second-layer wire electrode 206 are interconnected by plug electrodes 205 each penetrating through the interlayer insulating film 213.